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| HD151012 8-bit Binary Programmable Counter with Synchronous Preset Enable REJ03D0299-0200Z (Previous ADE-205-132 (Z)) Preliminary Rev.2.00 Jul.16.2004 Description The HD151012 has 8-bit binary down counter and D-type Flip Flop. The counter can set up to max 256 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider. Features * High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) * High output current Fanout of 10 LS TTL Loads * Wide operating voltage VCC = 2 to 6 V * Low supply current (Ta = 25C) ICC (Static) = 4 A (max) * Ordering Information Part Name HD151012TELL Package Type TSSOP-16 pin Package Code TTP-16DAV T Package Abbreviation Taping Abbreviation (Quantity) ELL (2,000 pcs/reel) Function Table Control Inputs CLR H X L H H X H L PR H L -- -- SPE Mode Generally count Synchronous preset Initialize of Q output Initialize of Q output Operation Description Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) Initialize of Q = "L" Initialize of Q = "H" Notes: 1. Synchronous preset (SPE) input can set max 256 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. H : High level L : Low level X : Immaterial -- : Irrespective of condition Rev.2.00, Jul.16.2004, page 1 of 13 HD151012 Pin Arrangement J0 1 J1 2 J2 3 J3 4 J4 5 J5 6 J6 7 GND 8 16 VCC 15 CLK 14 CLK 13 Q 12 PR 11 SPE 10 CLR 9 J7 (Top view) Pin Description Pin Name Input pins J0 to J7 CLK, CLK SPE PR Output pins CLR Q Pin Description Count data input for option Clock inputs CLK : Rise edge trigger CLK : Fall edge trigger Preset input for Jn data Preset input for D-type Flip Flop (Initialize "L" at Q output) Clear input for D-type Flip Flop (Initialize "H" at Q output) Output for D-type Flip Flop Absolute Maximum Ratings Item Supply voltage Input / output voltage VCC, GND current Output current / pin Power dissipation Storage temperature Input diode current VCC VIN/VOUT ICC, IGND IOUT PT Tstg IIK Symbol Ratings -0.5 to 7.0 -0.5 to VCC +0.5 50 25 500 -65 to 150 20 Unit V V mA mA mW C mA Output diode current IOK 20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal. Rev.2.00, Jul.16.2004, page 2 of 13 HD151012 Recommended Operating Conditions Item Supply voltage Input/output voltage Operating temperature Input rise/fall time*1 VCC = 2.5 V VCC = 4.5 V VCC = 5.5 V Note: Symbol VCC VIN/OUT Topr tr, tf 2 0 -40 0 0 0 Min -- -- -- -- -- -- Typ 6 VCC +85 1000 500 400 Max V V C ns Unit 1. This item guarantees maximum limit when one input switches. Logic Diagram J0 J1 J2 J3 J4 J5 J6 J7 J0 8-bit binary counter CLK CLK CLK J1 J2 J3 J4 J5 J6 J7 PR PR D CO SPE CK CLR SPE CLR Q Q Q Rev.2.00, Jul.16.2004, page 3 of 13 HD151012 Electrical Characteristics Ta = 25C Item High level input voltage Ta = -40 to 85C Test Conditions Symbol VCC Min Typ Max Min Max Unit VIH 2.0 1.5 -- -- 1.5 -- V J0 to J7 4.5 6.0 2.0 4.5 3.15 4.2 1.5 3.15 4.2 -- -- -- -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 4.5 6.0 4.31 5.80 0.0 0.0 0.0 0.17 0.18 -- -- -- -- -- -- -- 0.5 1.35 1.8 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 3.15 4.2 1.5 3.15 4.2 -- -- -- -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40.0 mA mA V VIN = VIH or VIL V V SPE PR, CLR CLK, CLK Low level input voltage VIL 6.0 2.0 4.5 6.0 2.0 4.5 J0 to J7 SPE PR, CLR CLK, CLK High level output voltage VOH 6.0 2.0 4.5 6.0 4.5 6.0 VIN = VIH or VIL IOH = -20 mA IOH = -4 mA IOH = -5.2 mA IOL = 20 mA Low level output voltage VOL 2.0 4.5 6.0 4.5 IOL = 4 mA IOL = 5.2 mA VIN = VCC or GND VIN = VCC or GND Input capacitance Supply current IIN ICC 6.0 6.0 6.0 Rev.2.00, Jul.16.2004, page 4 of 13 HD151012 Switching Characteristics (CL = 50 pF, tr = tf = 6 ns) SymItem Maximum clock frequency Output rise/fall time tTLH tTHL tPLH tPHL tPLH tPHL Pulse width (CLK, CLK, PR, CLR) Setup time (Jn - CLK, CLK) (SPE, CLK, CLK) Hold time (Jn - CLK, CLK) (SPE, CLK, CLK) Input capacitance Power dissipation capacitance*1 Note: CIN CPD ts tw bol fmax Ta = 25C Ta = -40 to 85C Test Conditions VCC Min Typ Max Min Max Unit 2.0 -- -- 4 -- 3 MHz 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 15 10 5 -- -- 36 -- 30 8 7 -- 35 -- -- 18 -- -- -- -- -- -- -- -- -- -- 5 48 20 24 75 15 13 300 60 53 150 30 25 -- -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 125 25 21 15 10 5 -- -- 16 19 95 19 16 380 75 65 185 38 32 -- -- -- -- -- -- -- -- -- 10 -- pF pF ns ns ns Propagation delay time CLK or CLK to Q PR or CLR to Q th ns 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. ICC (opr) = CPD * VCC * fIN + ICC Rev.2.00, Jul.16.2004, page 5 of 13 HD151012 Test Circuit VCC Input Pulse generator See Function Table VCC J0 J1 Output Q Zout = 50 Input Pulse generator Zout = 50 J7 CLK CLK SPE PR CLR CL Note: 1. CL includes probe and jig capacitance. Waveforms - 1 tw 6 ns tw 6 ns 90 % 90 % 50 % 50 % 10 % t PLH 90 % t PHL 90 % 50 % 10 % t THL CLK VCC CLK 10 % GND VOH Q 10 % 50 % t TLH VOL Rev.2.00, Jul.16.2004, page 6 of 13 HD151012 Waveforms - 2 6 ns 90 % 90 % 50 % 10 % 10 % ts VCC Jn GND 90 % 50 % CLK VCC CLK 10 % 10 % 6 ns GND VOH 50 % F/F Output *1 Internal delay VOL Waveforms - 3 6 ns 90 % 90 % 50 % 10 % th 10 % VCC Jn GND VCC CLK 50 % 90 % CLK 10 % 10 % 6 ns GND VOH 50 % F/F Output *1 Internal delay VOL Note: 1. F/F output is internal signal of IC. Rev.2.00, Jul.16.2004, page 7 of 13 HD151012 Waveforms - 4 6 ns 90 % 90 % 50 % 10 % 10 % ts VCC SPE GND 90 % 50 % CLK VCC CLK 10 % 10 % 6 ns GND VOH 50 % F/F Output *1 Internal delay VOL Waveforms - 5 6 ns 90 % 90 % 50 % 10 % th 10 % VCC SPE GND VCC CLK 50 % 90 % CLK 10 % 10 % 6 ns GND VOH F/F Output *1 50 % Internal delay VOL Note: 1. F/F output is internal signal of IC. Rev.2.00, Jul.16.2004, page 8 of 13 HD151012 Waveforms - 6 tf 90 % tr 90 % 50 % 10 % tw tf 90 % tr 90 % 50 % 10 % tw t PHL t PLH VCC CLR 50 % 10 % GND VCC PR 50 % 10 % GND VOH Q 50 % 50 % VOL Rev.2.00, Jul.16.2004, page 9 of 13 HD151012 Timing Chart CLK SPE J0 J1 J2 J3 J4 J5 J6 J7 (CO=SPE) CLR (Initialize of CLR) Q PR (Initialize of PR) Q Count 5 4 3 2 1 0 3 2 1 0 35 34 Rev.2.00, Jul.16.2004, page 10 of 13 HD151012 Example of Application Circuit AC Signal Generator for STN Type Liquid Crystal Panel Initialize counter: 50 J0 J1 J2 J3 J4 J5 J6 GND V CC CLK CLK Q PR SPE CLR J7 * * Note: When initializing output D-F/F apply "L" Rev.2.00, Jul.16.2004, page 11 of 13 HD151012 Timing Chart Example of AC Signal Generator 1 2 3 49 50 51 52 53 101 102 103 104 CLK SPE J0 J1 J2 J3 50 J4 J5 J6 J7 (CO=SPE) CLR Q PR Q Count 50 49 48 2 1 0 50 49 1 0 50 49 Rev.2.00, Jul.16.2004, page 12 of 13 HD151012 Package Dimensions As of January, 2003 Unit: mm 5.00 5.30 Max 16 9 4.40 1 *0.20 0.05 8 0.65 0.13 M 0.65 Max *0.15 0.05 1.0 6.40 0.20 0 - 8 0.50 0.10 1.10 Max 0.10 0.07 +0.03 -0.04 *Ni/Pd/Au plating Package Code JEDEC JEITA Mass (reference value) TTP-16DAV -- -- 0.05 g Rev.2.00, Jul.16.2004, page 13 of 13 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. 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